1. Field of the Invention
This invention relates to a semiconductor memory device for comparing a readout potential from a memory cell with a readout potential from a dummy memory cell (reference potential) and amplifying the difference therebetween, and more particularly to a cell array pattern layout of the semiconductor memory device.
2. Description of the Related Art
In an ultraviolet erasable and programmable read only memory (EPROM), a potential read out from a selected memory cell is compared with a potential read out from a dummy memory cell (reference potential) to determine whether stored data is "1" or "0". A circuit section used for data determination is constructed as schematically shown in FIG. 1. Data storing memory cells MC are arranged in a matrix form of m rows.times.n columns (only one of memory cells MC is shown in FIG. 1 as an example). One of m word lines WL is selected by means of a row decoder (not shown) and one of n bit lines BL is selected by means of column selector CS. In this way, one of memory cells MC whose control gate is connected to selected word line and whose drain is connected to selected bit line BL is selected. Memory cells MC arranged in a matrix form are connected to bias circuit/load circuit 21 via column selector CS. The potential of bit line BL which has been changed by data read out from selected memory cell MC is set to a preset level by means of bias circuit/load circuit 21. Potential VS thus set is supplied to one (comparison input terminal) of input terminals of differential amplifier 22 which receives at the other input terminal (reference input terminal) reference voltage VR from the dummy memory cell side circuit. The dummy memory cell side circuit is formed in substantially the symmetrical relation to a circuit section ranging from data storing memory cell MC to the comparison input terminal of differential amplifier 22 from the viewpoint of the circuit construction. The dummy memory cell side circuit includes dummy memory cell DMC, dummy bit line DBL, column selector equivalent transistor DCS, bias circuit/load circuit 23 and reference line (reference potential line) RL. The dummy memory cell side circuit supplies reference potential VR which is set to an intermediate potential level between the upper and lower levels of the potential of sense line SL varying according to data "0" or "1" stored in memory cell MC. Differential amplifier 22 determines data "1" or "0" by detecting whether or not potential VS of sense line SL is higher than potential VR of reference line RL. For simplifying the following explanation, a section including differential amplifier 22, a set of sense line SL and reference line RL, and a pair of bias circuits/ load circuits 21 and 23 is referred to as sense amplifier SA.
In the EPROM, in order to obtain an output which can be also used in a transistor transistor logic (TTL) circuit, an output buffer having a relatively large current driving ability is used. When the output buffer having the relatively large current driving ability is operated (in the data output mode), the potential of the power source line in the chip will fluctuate, that is, noise occurs. In the prior art, in order to suppress the noise, a method has been proposed in which the power source lines are separately arranged for the output buffer and the internal circuit. However, the noise cannot be sufficiently suppressed only by separation of the power source lines. Occurrence of the noise in the power source lines causes the potential of each node in the internal circuit supplied with power source voltage via the power source line to fluctuate. As a result, the potentials of bit line BL, dummy bit line DBL, sense line SL and reference line RL will also fluctuate.
If potential VS of sense line SL connected to the input terminal of differential amplifier 22 and potential VR of reference line RL fluctuate in synchronism with each other as shown in FIGS. 2A and 2B, for example, the potential level relation between potentials VS and VR will not be erroneously reversed. Therefore, determination of data "1" or "0" may be correctly effected. However, if the periods of fluctuations in potentials VS and VR are different from each other as shown in FIG. 2C, for example, the potential level relation between potentials VS and VR may be erroneously reversed in period .DELTA.T shown in FIG. 2C. As a result, stored data of "1" or "0" will be erroneously determined, and inverted data of the real data is output. In order to avoid such an erroneous operation, potentials VS and VR may be set to fluctuate with the same period as shown in FIGS. 2A and 2B. To this end, it becomes necessary to set the capacitances (including parasitic capacitances) associated with bit line BL and dummy bit line DBL equal to each other and set the capacitance on the comparison input terminal side (on the side of sense line SL) of differential amplifier 22 equal to that on the reference input terminal side (on the side of reference line RL).
However, with an increase in the integration density of the semiconductor memory device, the parasitic capacitance of data storing memory cell MC increases, thereby increasing the bit line load capacitance. Accordingly, it is necessary to increase the dummy bit line load capacitance. Addition of such a large capacitance to the dummy bit line causes a significant increase in the pattern area. If the bit line load capacitance caused by the data storing memory cell and the increased dummy bit line load capacitance caused by the data are out of balance, the noise will occur in the power source line, thereby causing an erroneous operation as described before.